1. Technical Field
The present invention relates to clock distribution in digital circuits. More particularly, the present invention relates to a controlled delay path for phase synchronizing an output clock signal to a reference input clock signal.
2. Description of the Prior Art
Modern digital electronic systems are comprised of a number of cooperating sequential logic circuits that each perform several routine operations, and that are each controlled by derivatives of a common clock signal. The clock signals must be synchronized at locations within the system if the system is to function optimally. Although the individual clock signals may have a common source, they often do not arrive at their intended destinations in proper synchronism, for example due to variations in signal propagation delay for each destination. Thus, combining several complex sequential logic circuits within a system presents a challenge with respect to synchronizing the time frames of each of the circuits with each other.
Because synchronous sequential logic circuits change states only at the rising or falling edge of a synchronous clock signal, proper circuit operation requires that any external input signals to the synchronous sequential logic circuit must occur with the proper set up time (t.sub.su) and hold time (t.sub.h) requirements relative to the designated clock edge. However, in a system comprised of sequential logic circuits having a master system clock that operates the several diverse system circuits there is a problem with skew between the system clock and the destination clock signals propagated through the various circuits.
As integration levels of microelectronic circuits and system complexity continues to increase, the routing or distribution of a master system clock becomes more critical. This problem is exacerbated in view of ever increasing clock rates. Thus, clock distribution in a complex integrated circuit requires careful selection of a routing scheme, including such considerations as distribution topography across the circuit, propagation delays in routing the clock signal to all elements on the circuit, desired set up and hold times, and variations in system design parameters, such as system clock rate, that can affect circuit operation.
One solution to this problem is to employ a voltage controlled oscillator in a phase-locked loop to adjust the various signals, such that the edges of the internal clock signals are aligned with those of the master or reference clock signal. The phase-locked loop provides feedback that is used to null out clock distribution delays within the circuit by comparing the phase of a first signal with that of a second signal. The difference between the two signals is used in a feedback control system to bring the first and second signals into a fixed phase relation. With regard to a clock distribution scheme, the first signal is typically a reference signal derived from the master system clock, and the second signal is typically a controlled signal of variable frequency.
Although analog phase-locked loops were first used in clock distribution circuits, digital phase-locked loops have gained wider acceptance. In such digital phase-locked loops, a digital phase detector is used, although the phase-locked loop architecture is otherwise composed of analog elements, i.e. voltage controlled oscillator, loop filter. See for example A. Wray, Clock Synchronization Circuit for Digital Communications System, UK Patent Application No. GB 9117645 (15 Aug. 1992) which discloses a burst-mode TDMA system including a clock synchronization circuit that provides a clock signal having a frequency that is greater than the signal frequency of the received data signal. An AND gate and divider logically combine the clock signal with the received data signal to provide a synchronization signal for the digital communications system. The synchronization signal is compared with the received data signal and an error signal is generated in response to the difference. Delay circuitry successively introduces delays to the clock signal to reduce the error in response to transitions of the synchronization signal until the synchronization and received data signals are synchronized.
See, also M. Alsup, C. Dobbs, E. Haddad, C. Moughanni, Y. Wu, Digital Phase Lock Clock Generator Without Local Oscillator, U.S. Pat. No. 5,173,617 (22 Dec. 1992) (digital phase-locked loop including a phase detector that controls, and an up-down counter to program, an increase/decrease in a tapped delay line); J. Hjerpe, D. Russell, R. Young, All Digital Phase-Locked Loop, U.S. Pat. No. 5,109,394 (28 Apr. 1992) (digital phase-locked loop for synchronizing an output clock with a reference clock signal, including a multiple-tap, digital delay chain to delay the output clock signal); D. Preslar, Digital Phase Comparator With Improved Sensitivity For Small Phase Differences, U.S. Pat. No. 4,322,643 (30 Mar. 1982) (digital phase comparator for eliminating the dead zone in the phase correction means of a phase-locked loop); A. Efendovich, Y. Afek, C. Sella, Z. Bikowsky, Multi-Frequency Zero-Jitter Delay-Locked Loop, IEEE 1993 Custom Integrated Circuits Conference (1993) (all digital delay-locked loop); T. Lee. K. Donnelly, J. Ho, J. Zerbe, M. Johnson, T. Ishikawa, A 2.5 V Delay-Locked Loop for an 18 Mb 500 MB/s DRAM, IEEE International Solid-State Circuits Conference (1994) (receive delay-locked loop); and A. Waizman, A Delay Line Loop for Frequency Synthesis of De-Skewed Clock, IEEE International Solid-State Circuits Conference (1994) (delay line loop clock generator circuit used for frequency synthesis multiplication of a de-skewed clock).
Modern system designs may specify a wide range of system clock rates, e.g. from 10-MHz or less to 100-MHz or more. When it is considered that clock distribution may consume 20% or more of a clock period, it is clear that clock delays, while not critical at slower clock rates (for example at 10-MHz, where a clock delay of 5 nsec is about 5% of a clock period of 100 nsec), become extremely critical at faster clock rates (for example at 100-MHz, where a clock delay of 5 nsec (i.e. 50%) is unacceptable when compared to a clock period of 10 nsec). While a phase-locked loop may include a series of tapped delays, such as buffers, voltage controlled delays, shift registers, and the like, to extend its range of operation, such expedients take up considerable space, while providing only a minimal amount of range of operation extension. Thus, while a phase-locked loop may be useful for a narrow range of system clock rates, it is not practical for complex integrated circuits that are intended for a wide variety of system applications over a broad range of system clock rates.
There is no need for a phase-locked loop having a voltage controlled oscillator if the system provides a master clock of the correct frequency, because the fundamental problem is aligning the edges of the system clock precisely with those of the internal device clocks such that all system elements operate in synchronism. Accordingly, there is a need to synchronize (i.e. de-skew or match rising edges) output clock signals with that of a master clock in a precise and stable manner over a wide range of operating parameters and reference clock frequencies, so as to cancel uncertainty introduced by internal clock distribution delays.